1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for stacking multiple semiconductor devices and packaging the same.
2. Description of the Related Art
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Still another technical challenge associated with stacked semiconductor chips is testing.
A process flow to transform bare semiconductor wafers into collections of semiconductor chips and then mount those semiconductor chips on an interposer or circuit board involves a large number of individual steps. Because the processing and mounting of a semiconductor chip proceeds in a generally linear fashion, that is, various steps are usually performed in a specific order, it is desirable to be able to identify defective parts as early in a flow as possible. In this way, defective parts may be identified so that they do not undergo needless additional processing. If, for example, the first semiconductor chip mounted to a circuit board is revealed to be defective only after several other semiconductor chips are stacked thereon, then all of the material processing steps and the materials associated with the later-mounted chips may have been wasted. Conversely, it is desirable to be able to remove a defective chip from a stack or circuit board without necessarily impacting the integrity of any remaining chip(s).
Many conventional stacked chips are interconnected by way of solder bumps. To non-destructively remove one chip without impacting the viability of the solder bumps associated with a remaining chip is a technical challenge. Furthermore, some types of semiconductor chips may be more prone to post-fabrication faults than others.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.